The present invention relates generally to semiconductor on insulator processes, and more particularly to a method of forming buried interconnects on wafers and devices including the same.
Conventional or bulk semiconductor devices include transistors, and other semiconductor devices, formed in a semiconductor substrate by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity, plus a field oxide to prevent surface inversion. Transistor gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). Each of these must be electrically isolated from the others to avoid shorting the circuits.
A relatively large amount of surface area of bulk semiconductor logic circuits is needed for the electrical isolation of the various FETs which is undesirable because it inhibits transistor packing density. Additionally, junction capacitance between the source/drain and the bulk substrate slows the speed at which a device using such transistors operates.
In order to deal with the junction capacitance problem and circuit density, SOI technology has been employed. For example, one method of forming an SOI wafer is using conventional oxygen implantation techniques to create an insulating buried oxide layer at a predetermined depth below the surface of a bulk semiconductor wafer. The implanted oxygen combines with the bulk silicon to form silicon oxide as is well known in the art. A second method of forming an SOI wafer includes depositing an insulating layer of silicon oxide on the surface of a first wafer and then bonding the first wafer to a second wafer using a heat fusion process.
Utilizing SOI technology, an SOI FET includes a source region and a drain region of one semiconductor type on opposite sides of a channel region of the opposite semiconductor type. The SOI FET is isolated by etching a trench around an area, filling the trench with oxide and planarizing this oxide. The area is an island of semiconductor material formed from a semiconductor layer above an insulating buried oxide layer. The appropriate portions of the island are doped to form the source, drain and channel regions. The SOI FET will occupy less surface area on the substrate and will have a lower junction capacitance than an equivalent bulk semiconductor FET because of the insulating trench and the insulated buried oxide layer. This structure improves clock speeds and increases the number of circuit elements that can be placed at a given area.
Unfortunately, die size reduction is also inhibited by the interconnection of the FETS or other devices with each other and other circuit elements. For example, typical interconnections of known complimentary MOS (CMOS) devices are structured to interconnect both P-channel and N-channel FETs and conventionally are metal layers above the bulk substrate. The presence of the metal layers above the bulk substrate inhibits size reduction.
Accordingly, there is a strong need in the art to have an alternative to metal layers above the bulk substrate to reduce the die area occupied by interconnects.
An object of the present invention is to provide a semiconductor on insulator structure including a plurality of active regions formed on an insulator layer, a plurality of isolation trenches formed between the active regions for substantially isolating adjacent active regions, and at least one interconnection trench that includes an interconnect formed at the bottom of the at least one interconnection trench for electrically connecting a first active region of the active regions to a second active region of the active regions.
Another object of the present invention is to provide a method of forming a semiconductor on insulator structure including forming trenches in a semiconductor material, some of the trenches extending through the semiconductor material to an insulation layer and some of the trenches extending to an intermediate depth; and processing a bottom portion of the trenches extending to the intermediate depth to make the bottom portion electrically conductive.
Another object of the present invention is to provide a method of forming a semiconductor on insulator structure including providing a silicon layer including active regions on an insulation layer, forming a silicon oxide layer on the silicon layer by oxidation, forming a silicon nitride layer on the silicon layer by nitride deposition, forming a trench mask over the silicon nitride layer, etching through the silicon oxide and silicon nitride layers and into the silicon layer with a timed etch, providing an interconnect mask over a portion of the etched semi-conductor layer with the timed etch, etching the etched silicon layer not covered by the interconnect mask with a high silicon to nitride selectivity etch to isolate at least two active regions from each other, stripping the interconnect mask, oxidizing surface silicon exposed by the high silicon to nitride selectivity etch and the timed etch by oxidation, anisotropically etching a portion of the oxidized surface silicon with an anisotropic oxide etch, siliciding the area silicon to form an interconnect, depositing an oxide layer and polishing the oxide layer to the silicon nitride layer, and removing the silicon nitride layer.